1. Field of the Invention
The present invention relates to a memory device, and in particular, to a current controlling circuit for a memory device that controls current consumption.
2. Background of the Related Art
FIG. 1 illustrates the construction of a 16M related Dynamic Random Access Memory (RAM) formed of eight 2M bit memories. FIG. 2 illustrates a 2M bit DRAM of FIG. 1. Each 2M bit memory is formed of a memory block 101 having eight 256 bit memory cell arrays, a signal amplifying block 102 formed of four main amplifiers M/A1 through M/A4 for amplifying the data from the memory block 101 and a signal amplifying controller 103. The signal amplifying controller 103 outputs enable signals RMA0 through RMA3 to control the operation of the signal amplifying block 102.
As shown in FIG. 3, the four main amplifiers M/A1 through M/A4 each include a pre-charge circuit 111 for equalizing input lines CIOT and CIOB in accordance with an equalization signal EQB. A first differential amplifying circuit 112 is for differentially amplifying the signals from the input lines CIOT and CIOB when a read enable signal RMA is activated. A second differential amplifying circuit 113 is for differentially amplifying the output signal from the first differential amplifying circuit 112 when the read enable signal RMA is activated, and a latch unit 114 is for latching the output signal from the second differential amplifying circuit 113 and outputting an amplifying signal MOT/MOB.
The pre-charge circuit 111 is connected between the input lines CIOT and CIOB by connecting PMOS transistor P1 in parallel with PMOS transistors P2, and P3 between the input lines CIOT and CIOB. The equalization signal EQB is transmitted to the gates of the PMOS transistors P1 through P3, and an output signal VMP is outputted at the connection point between the PMOS transistors P2 and P3.
In the first differential amplifying circuit 112, NMOS transistors N1 through N3 and N4 through N6 are respectfully connected to PMOS transistors P4, P5 and P6, P7, which form a current mirror, to form a differential amplifier. The input line CIOT is connected to the gates of the NMOS transistors N1 and N5, respectively, and the input line CIOB is connected to the gates of the NMOS transistors N2 and N4, respectively. The read enable signal RMA is transmitted to the gates of the NMOS transistors N3 and N6. The connection point between the PMOS transistor P5 and the NMOS transistors N2 and the connection point between the PMOS transistor P7 and NMOS transistor N5 are respectively connected with the input terminals of the second differential amplifying circuit 113.
In the second differential amplifying circuit 113, the drain of the NMOS transistor N7, which receives a second output signal from the first differential amplifying circuit 112, is commonly connected to the drain of the PMOS transistor P8 and the gate of the PMOS transistor P9. The source of the PMOS transistor P8 receives a voltage Vcc. Thus, a first output terminal is formed.
The gate of the NMOS transistor N8 receives a first output signal from the first differential circuit 112. The drain of the NMOS transistor N8 is commonly connected with the gate of the PMOS transistor P8 and the drain of the PMOS transistor P9. The source of the PMOS transistor P9 receives the voltage Vcc. Thus, a second output terminal is formed. The drains of PMOS transistors P10 through P13 are respectively connected with the gates and drains of the NMOS transistors N7 and N8. The gates of PMOS transistors P10-P13 receive a read enable signal RMA.
In the latch unit 114, an input terminal of a NAND-gate NA1 receives a first output signal from the second differential amplifying circuit 113. The output signal from the NAND-gate NA1 is inputted into an input terminal of a NAND-gate NA2. Another input terminal of the NAND-gate NA2 receives a second output signal from the second differential amplifying circuit 113. Further, the output signal from the NAND-gate NA2 is inputted into another input terminal of the NAND-gate NA1. Then, the output signals from the NAND-gates NA1 and NA2 are respectively inputted into inverters IN1 and IN2, which output output signals MOT and MOB.
Transmission gates TG1, TG2 are respectively connected between the first and second output terminals of the first and second differential amplifying circuits 112 and 113. The transmission gates TG1 and TG2 are pre-charged in accordance with equalization signals EQ and EQB.
As shown in FIG. 4, the signal amplifying controller 103 includes inverters IN3 and IN4 for inverting input signals BYi and BYj. A NAND-gate NA3 NANDs the output signals from the inverters IN3 and IN4. An inverter IN5 is for inverting the output signal from the NAND-gate NA3 and outputting a read enable signal RMA0. A NAND-gate NA4 NANDs the input signal BYj and the output signal from the inverter IN3. An inverter N6 is for inverting the output signal from the NAND-gate NA4 and outputting a read enable signal RMA1. A NAND-gate NA5 NANDs the input signal BYi and the output signal from the inverter IN4. An inverter IN7 is for inverting the output signal from the NAND-gate NA5 and outputting a read enable signal RMA2. A NANDgate NA6 NANDs the input signals BYi and BYj, and an inverter IN8 inverts the output signal from the NAND-gate NA6 to output a read enable signal RMA3.
The operation of the related art circuit for a memory device will now be described. First, when a normal read operation is performed, the data stored in the eight 256 bit memory cell arrays of the memory block 101 are carried on a global data line through a local data line connected to both ends of the 256 bit memory cell array and are transmitted to the main amplifiers M/A1 through M/A4 of the signal amplifying block 102.
At this time, the signal amplifying controller 103 logically operates word line input signals BYi and BYj shown in FIGS. 5C and 5D to output a read enable signal RMA as shown in FIG. 5E to the signal amplifying block 102. The read enable signal RMA0 is outputted through the inverters IN3 and IN4, the NAND-gate NA3, and the inverter IN5 for enabling the main amplifier M/A1. The read enable signal RMA1 is outputted through the inverter IN3, the NAND-gate NA4, and the inverter IN6 for enabling a main amplifier M/A2. The enable signal RMA2 is outputted through the inverter IN4, the NAND-gate NA5, and the inverter IN7 for enabling a read main amplifier M/A3. The read enable signal RMA3 is outputted through the NAND-gate NA6 and the inverter IN8 for enabling a main amplifier M/A3.
Therefore, when the read enable signals RMA0 through RMA3 of the signal amplifying controller 103 are inputted into the signal amplifying block 102, only one or two of the main amplifiers M/A1 through M/A4 are operated. The data selected from the memory block 101 is amplified and then outputted.
A test mode operation is performed to reduce a testing time by reducing the number of addresses. In particular, a 16M DRAM is operated like a 1M DRAM by operating all the main amplifiers M/A1 through M/A4 of the signal amplifying block 102.
The data read by the memory block 101 is carried on the global data line through the local data line in accordance with an address and is transmitted to the signal amplifying block 102. At this time, the signal amplifying controller 103 logically combines the input signals BYi and BYj, outputs the read enable signals RMA0 through RMA3 to the signal amplifying block 102, respectively, and operates the main amplifiers M/A1 through M/A4. The main amplifiers M/A1 through M/A4 amplify the data from the memory block 101, so that the 16M DRAM is operated like the 1M DRAM.
The operation of the main amplifiers M/A1 through M/A4 in the normal mode and the test mode will now be described with reference to FIG. 3 and FIGS. 5A through 5G. As shown in FIGS. 5A and 5B, when the level of an equalization signal EQB is changed from high to low, in the pre-charge circuit 111 of the main amplifiers M/A1 through M/A4, the PMOS transistors P1 through P3 are turned on. Thus, the input terminals CIOT and CIOB are pre-charged to high level as shown in FIG. 5F.
At this time, the read enable signal RMA is low. Accordingly, in the differential amplifying circuit 113 of the main amplifiers M/A1 through M/A4, the PMOS transistors P12 and P13 are turned on. Thus, the output terminal is pulled up by the voltage Vcc, and the latch 114 maintains a previous output state.
When the signal amplifying controller 103 outputs the read enable signal RMA to the signal amplifying block 102 by receiving the word line signals BYi and BYj, one or two of the main amplifiers M/A1 through M/A4 is/are selected in the read mode, and all the main amplifiers M/A1 through M/A4 are selected in the test mode. For each main amplifier selected from the main amplifiers M/A1 through M/A4 in accordance with the read enable signal RMA, in the first and second differential amplifying circuits 112 and 113, the NMOS transistors N3, N6, and N9 are turned on.
As shown in FIGS. 5A and 5B, when the equalization signal EQB changes from low to high level, the operation of the pre-charge circuit 111 of the main amplifiers M/A1 through M/A4 is stopped. Then, the data from the input terminals CIOT and CIOB are inputted into the first differential amplifying circuit 112.
On the assumption that the level of the data from the input terminal CIOT is higher than that of the data from the input terminal CIOB, in the first differential amplifying circuit 112, the NMOS transistors N1 and N5 are turned on. The NMOS transistors N2 and N4 are turned off. Thus, the current flowing at the PMOS transistors P4 and P5, which form a current mirror, is transmitted to the second differential amplifying circuit 113. The PMOS transistors P6 and P7, which form a current mirror, maintain a turned-off state, whereby the current is not transmitted to the second differential amplifying circuit 113.
In the second differential amplifying circuit 113, the NMOS transistor N7 is turned on. Accordingly, the PMOS transistor P9 is turned on, the NMOS transistor N8 is turned off and the PMOS transistor P8 is turned off. Thus, only the current flowing at the PMOS transistor P9 is transmitted to the latch unit 114.
In the latch unit 114, the output signal from the NAND-gate NA2 becomes high. Then, the output signal from the NAND-gate NA1 becomes a low level signal. Accordingly, the high signal MOT is outputted from the inverter IN1, and the low level signal MOB is outputted from the inverter IN2. The output timing of the output signals MOT and MOB from the latch unit 114 is shown in FIG. 5G.
If the level of the data from the input terminal CIOT is assumed to be lower than that of the data from the input terminal CIOB, the first and second differential amplifying circuits 112 and 113 are then operated in the reverse sequence. In this case, the low signal MOT and the high signal MOB are outputted from the latch unit 114.
However, in the related art circuit for a memory device, the main amplifiers are partially selected. When the number of concurrently operated main amplifiers is decreased to 1/2 or 1/4, the power supply becomes unstable because of an over current. In addition, in the test mode, since all the amplifiers are operated, the operational current is increased by two times or four times, which causes unstable operation. In this case, the operational accuracy of the test result is degraded.